The invention relates to a logic circuit which has a simple circuit configuration and operates at a high speed. More specifically, the present invention relates to a Complementary Schottky Transistor Logic Circuit (which will be hereinafter referred to as the CSTL circuit).
The basic concept of the CSTL circuit employed in the present invention has been disclosed in in Japanese Utility Model Application Laid-Open No. 169454/79 entitled "Logic Circuit", laid open on Nov. 30, 1979; and the present invention concerns interconnection of such CSTL circuits and setting of load conditions associated therewith.
As logic circuits using bipolar transistors, in general, TTL, STTL and ECL circuits have become well known. Although these circuits operate at higher speeds, they consume large power and require a large circuit area. An I.sup.2 L circuit which has been proposed recently, operates at a lower speed though it needs a substantially smaller circuit area.
On the other hand, there has been suggested a C.sup.3 L logic circuit which is intended to bridge the gap between the TTL circuits and the I.sup.2 L with respect to the performance and the circuit area (ISSCC '75 Session 14.4 A New Approach to Bipolar LSI; C.sup.3 L).
The basic circuit configuration of the C.sup.3 L circuit is shown in FIG. 1A and has the following features.
(1) The C.sup.3 L circuit is similar to the I.sup.2 L circuit and has a pnp transistor P1 at its base input side and a driving transistor (npn transistor) N1. Because the driving transistor N1 is in the downward- or forward-operation mode, it operates at a high speed.
(2) The driver transistor N1 has two sorts of Schottky diodes D1 and D2 (and/or D2' and/or D2") for clamp and output, respectively.
(3) The C.sup.3 L circuit has one input IN and a plurality of outputs OUT1 to OUT3.
In FIG. 1A, a supply voltage is denoted by V.sub.EE and a bias voltage for a base of the load transistor P1 is represented by V.sub.BB.
FIG. 1B shows a logic circuit which comprises three basic C.sup.3 L circuits of FIG. 1A and includes pnp transistors P11, P12, P13, npn transistors N11, N12, N13, and Schottky diodes D21, D22, D23 for output. A clamping Schottky diode is provided in each npn transistor but is omitted in FIG. 1B. More specifically, each of the transistors N11, N12 and N13 in FIG. 1B consists of such an npn transistor N1 and a clamping Schottky diode D1 as shown in FIG. 1A, and is represented by a symbol " ".
The major defect of the C.sup.3 L logic circuit is that the circuit requires two types of Schottky diodes. In the operation of the C.sup.3 L circuit, logic swing .DELTA.V is expressed in terms of V.sub.F1 and V.sub.F2 as follows. EQU .DELTA.V=V.sub.F1 -V.sub.F2
where, V.sub.F1 represents the forward voltage of the diode D1 and V.sub.F2 represents the forward voltage of the diode D2. In the above equation, V.sub.F1 must be always greater than V.sub.F2.
In order to make sure to always satisfy the above relationship and condition, the two types of Schottky diodes must be fabricated with different metals to each other. In the case of the C.sup.3 L circuit disclosed in 1975, the diodes D1 is formed with PtSi and the diode D2 is with Ti.
In fabrication of integrated circuits of such logic circuits, the necessity to use two types of interconnection metals will involve many undesirable problems. More specifically, a Schottky diode basically consists of a metal in contact with silicon (Si) and its interconnection is established by making an electrode hole usually called a contact hole, evaporating the metal and then providing patterning. In the case that two types of metals are required, as for example, in the C.sup.3 L circuit fabrication; first, the operations of contact hole making, metal evaporation and patterning must be provided with respect to one of the two types of diodes, and thereafter the similar operations must be provided for the other diodes, of course, by use of different metal from the former diode. This means that this C.sup.3 L circuit fabrication requires three additional steps, i.e. a total of three steps of contact making, evaporation and patterning, when compared to other logic circuit fabrication in which one type of metal is necessary. In addition, the C.sup.3 L circuit fabrication requires two additional masks for the contact hole and patterning. Especially, in the practical C.sup.3 L circuit fabrication, four types of metals of PtSi, Ti, Pt and Al (or Au) are used, which results in many complicated steps.
Such complicated production steps and the increased number of masks will undesirably contribute to the increased cost and reduced yield in fabrication of the integrated circuit.